Hdlwise: Verilog & VHDL
Score-based assessment (medium risk, 49/100). No analyst review available.
Analysis record
- Analysed
- 2 days ago
- Version
- v1.0.0
- Artifact
- SHA256 4ED…C14
- Source
- Findings (non-IoC)
Evidence ledger
Ranked by severity · findings with a source location link to the code viewer
YARA Rule Matches
9 rules| Severity | Rule | Hits | Files | Metadata |
|---|---|---|---|---|
| LOW | postinstall file download | 8 | jetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-formatjetbrain-plugin-hdlwise/docker/Dockerfilejetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-format +5 more | - |
| LOW | postinstall crypto operations | 8 | jetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-formatjetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-formatjetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-ls +5 more | - |
| LOW | postinstall network communication | 12 | jetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-lsjetbrain-plugin-hdlwise/language-servers/vhdl_libraries/ieee2008/std_logic_1164-body.vhdljetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-lint +9 more | - |
| LOW | postinstall file manipulation | 39 | jetbrain-plugin-hdlwise/language-servers/vhdl_libraries/vital2000/prmtvs_b.vhdljetbrain-plugin-hdlwise/language-servers/vhdl_libraries/ieee2008/numeric_std.vhdljetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-ls +36 more | - |
| LOW | postinstall system command | 21 | jetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-lsjetbrain-plugin-hdlwise/language-servers/vhdl_libraries/ieee2008/float_generic_pkg.vhdljetbrain-plugin-hdlwise/language-servers/vhdl_libraries/ieee2008/float_generic_pkg-body.vhdl +18 more | - |
| LOW | postinstall registry modification | 7 | jetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-formatjetbrain-plugin-hdlwise/language-servers/linux-x64/vhdl_lsjetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-format +4 more | - |
| LOW | postinstall obfuscation | 12 | jetbrain-plugin-hdlwise/language-servers/vhdl_libraries/vital2000/prmtvs_b.vhdljetbrain-plugin-hdlwise/language-servers/vhdl_libraries/vital2000/memory_b.vhdljetbrain-plugin-hdlwise/language-servers/linux-x64/verible-verilog-lint +9 more | - |
| LOW | postinstall persistence mechanism | 12 | jetbrain-plugin-hdlwise/language-servers/vhdl_libraries/vital2000/prmtvs_b.vhdljetbrain-plugin-hdlwise/language-servers/vhdl_libraries/vital2000/timing_p.vhdljetbrain-plugin-hdlwise/language-servers/linux-arm64/verible-verilog-ls +9 more | - |
| LOW | PM Zip with js | 1 | jetbrain-plugin-hdlwise/lib/jetbrain-plugin-hdlwise-1.0.0-searchableOptions.jar | - |
Network Indicators
Concrete URLs, domains, IPs, emails, and hashes extracted from the analyzed artifact.
Loading network indicators
IoC detail rows are loaded outside the initial page render.
Publisher Evidence
Lowkitss-tech
Publisher identity, store signals, distribution reach, and warning signals used for context. Treat this as supporting evidence, not a clean bill of health.
12 evidence rows available.
Finding Categories
YARA Rules Matched
9 rules(120 hits)Security Analysis Summary
Security Analysis Overview
Hdlwise: Verilog & VHDL is a JetBrains Marketplace extension published by kitss-tech. Version 1.0.0 has been analyzed by the Risky Plugins security platform, receiving a risk score of 48.59/100 (MEDIUM risk) based on 831 security findings.
Risk Assessment
This extension presents moderate security risk. Several findings were detected that may warrant attention. Users should carefully review the permissions and findings before installation.
Findings Breakdown
- Medium: 640 finding(s)
- Low: 120 finding(s)
What Was Analyzed
The security assessment covers multiple analysis categories:
- Malware Detection: YARA rule matching against 2,400+ malware signatures
- Secret Detection: Scanning for exposed API keys, tokens, and credentials
- Static Analysis: Code-level security analysis for common vulnerability patterns
- Network Analysis: Detection of suspicious network communications and endpoints
- Obfuscation Detection: Identification of code obfuscation techniques
Developer Information
Hdlwise: Verilog & VHDL is published by kitss-tech on the JetBrains Marketplace marketplace. The extension has approximately 1 users.
Recommendation
Exercise caution with this extension. Review the detailed findings and ensure the requested permissions align with the extension's stated functionality before installation.
About This Extension
Frequently Asked Questions
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